This invention relates generally to an electronic energy consumption metering circuit capable of being fabricated on an integrated circuit chip, and more particularly to the compensation of charge injection offset caused by metal oxide semiconductor (MOS) analog switches and DC offsets caused by multipliers and the like employed in such circuit.
Electronic circuits for measuring electrical energy consumption in an electrical system, such as an AC power distribution system, are well known. Typically, these circuits may comprise a switched time division multiplier for multiplying two signals representative of the instantaneous current and voltage in the electrical system and for providing a product signal which is representative of the instantaneous power being supplied by the electrical system. The product signal from the multiplier may be integrated in an integrator circuit to provide a signal representative of the average power or energy consumption, and this signal may be converted to a pulse train in which each pulse represents a predetermined unit quantity of energy. The pulses may be counted or accumulated to provide a measure of total energy consumption. This basic technique of electronic metering is described, for example, in U.S. Pat. No. 3,955,138 which issued to the present inventor, and various electronic metering circuits employing this technique are disclosed in other patents of the present inventor, including U.S. Pat. Nos. 4,066,960; 4,217,546; 4,485,343; 4,495,463; and 4,535,287. The foregoing patents are all commonly assigned with the present invention to General Electric Company, and are incorporated by reference herein. This application is also related to the commonly assigned application of the present inventor, Ser. No. 010613 pending filed concurrently herewith.
While the electronic circuits disclosed in the foregoing patents are capable of accurate metering and perform satisfactorily, it is desirable to improve their accuracy and reduce their cost and size by fabricating each of the respective circuits on a respective solid state semiconductor monolithic integrated circuit chip. It is relatively easy to fabricate components such as analog switches, amplifiers, logic elements, etc. on silicon chips using, for example, MOS technology. The present inventor's commonly assigned copending application Ser. No. 812,369, now U.S. Pat. No. 4,682,102, filed Dec. 23, 1985, and Ser. No. 947,114, filed Dec. 29, 1986, which applications are incorporated by reference herein, disclose improved switched-capacitor electronic metering circuits which are capable of being fabricated entirely on integrated circuit chips. These metering circuits have an automatic offset error correction loop which employs dual slope integration that substantially compensates for system offset error voltages. The analog switches employed in the circuits comprise metal oxide semiconductor field effect transistors (MOSFETs) and introduce transient offset error voltages due to charge injection. In addition, the multiplier used in the circuits, and possibly the sensors which monitor the line current, have DC offsets. These may not be fully compensated by the system offset correction loop. These uncompensated offset voltages introduce error and limit accuracy of the metering circuits.
It is desirable to eliminate or reduce the effects of charge injection offset caused by MOS analog switches and the DC offset voltages of multipliers and the like in order to improve dynamic performance and accuracy of switched-capacitor electronic metering circuits, and the present invention is directed to this end.